The present invention relates to a memory circuit and more particularly to a static memory circuit of an asynchronous type.
Asynchronous type static memories are known and widely used as high speed memories. The asynchronous type static memory operates without receiving any clock signal from the outside memory; it generates timing signals for controlling the respective sections in accordance with changes in address signals and a write enable signal. However, in the prior art the respective peripheral circuits of the memory are controlled in the same manner both in a read operation and in a write operation, and a sense amplifier is also enabled in a write operation even though a function of the sense amplifier is not necessary in a write operation, resulting in large power consumption.
Also, it is frequently required to output the same data written into a selected memory cell to an output terminal. To that end, after the write operation, the same word line is selected again to perform a read operation on the same memory cell which was selected in the previous write operation. Thus, the reading of the written data cannot be performed at a high speed and such read operation also has a large power consumption.